Silicon Labs /Series0 /EFM32TG /EFM32TG110F32 /DAC0 /CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DIFF)DIFF 0 (SINEMODE)SINEMODE 0 (CONTINUOUS)CONVMODE 0 (DISABLE)OUTMODE 0 (OUTENPRS)OUTENPRS 0 (CH0PRESCRST)CH0PRESCRST 0 (1V25)REFSEL 0 (NODIVISION)PRESC0 (8CYCLES)REFRSEL

PRESC=NODIVISION, OUTMODE=DISABLE, REFRSEL=8CYCLES, REFSEL=1V25, CONVMODE=CONTINUOUS

Description

Control Register

Fields

DIFF

Differential Mode

SINEMODE

Sine Mode

CONVMODE

Conversion Mode

0 (CONTINUOUS): DAC is set in continuous mode

1 (SAMPLEHOLD): DAC is set in sample/hold mode

2 (SAMPLEOFF): DAC is set in sample/shut off mode

OUTMODE

Output Mode

0 (DISABLE): DAC output to pin and ADC disabled

1 (PIN): DAC output to pin enabled. DAC output to ADC and ACMP disabled

2 (ADC): DAC output to pin disabled. DAC output to ADC and ACMP enabled

3 (PINADC): DAC output to pin, ADC, and ACMP enabled

OUTENPRS

PRS Controlled Output Enable

CH0PRESCRST

Channel 0 Start Reset Prescaler

REFSEL

Reference Selection

0 (1V25): Internal 1.25 V bandgap reference

1 (2V5): Internal 2.5 V bandgap reference

2 (VDD): VDD reference

PRESC

Prescaler Setting

0 (NODIVISION): undefined

REFRSEL

Refresh Interval Select

0 (8CYCLES): All channels with enabled refresh are refreshed every 8 prescaled cycles

1 (16CYCLES): All channels with enabled refresh are refreshed every 16 prescaled cycles

2 (32CYCLES): All channels with enabled refresh are refreshed every 32 prescaled cycles

3 (64CYCLES): All channels with enabled refresh are refreshed every 64 prescaled cycles

Links

() ()